1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to an electrostatic discharge (ESD) protection circuit on a semiconductor device and a method for forming the same.
2. Description of the Related Art
Damage from electrostatic discharge (ESD) is a significant failure mechanism in modern integrated circuits, particularly as integrated circuit (IC) physical dimensions continue to shrink to the sub-micron range. Electrically, an ESD event occurs upon contact of one or more of the terminals of an IC terminal with a body that is statically charged to a high voltage (up to on the order of thousands of volts). This level of static charge is readily generated by the triboelectric effect and other mechanisms acting upon humans or manufacturing equipment. Upon contact, the IC discharges the charged body through its active devices and DC current paths. If the amount of charge is excessive, however, the discharge current density can damage the IC so that it is no longer functional, or so that it is more prone to later life failure. ESD damage thus is a cause of yield loss in manufacturing, and also poorer reliability in use.
It is common practice in the art to implement, into each IC, ESD protection devices connected to the external terminals of the circuit. ESD protection devices are designed to provide a current path of sufficient capacity to safely discharge the charge applied thereto by a charged body in an ESD event, but to not inhibit the functionality of the IC in normal operation. The addition of ESD protection devices necessarily add parasitic effects that degrade circuit performance; in some cases such as series resistors, the ESD protection devices directly add delay to electrical performance. Accordingly, a desirable goal for ESD protection devices is to provide a high capacity current path, which is readily triggered during an ESD event but which can never trigger during normal operation, and which presents minimal effect on circuit performance.
FIG. 1 is a schematic, cross-sectional view of a conventional ESD protective circuit.
A substrate 100 is provided. A plurality of field oxide layers 102 are formed in the substrate 100 to serve as isolation structures, which define out an active region. These field oxide layers 102 can be formed either through a LOCOS (local oxidation of silicon) process or by first performing an STI (shallow trench isolation) process to form trenches in the substrate 100 and then performing a CVD (chemical-vapor deposition) process to deposit oxide into the trenches. A gate oxide layer 112, a polysilicon layer 114, a spacer 116, and a source/drain region 118 with a lightly doped drain (LDD) region (the source/drain region 118 comprises an N+ doped region and an N− doped region) are sequentially formed on the substrate 100. Subsequently, self-aligned silicide (salicide) layers 120 are respectively formed on the polysilicon layer 114 and on the source/drain region 118 by a salicide process. Next, a patterned photoresist is respectively formed to cover the active region. A portion of the salicide layer exposed by the patterned photoresist is stripped away by dry etching until a portion of the source/drain region is exposed. The photoresist is then removed. Subsequently, a thick inter-layer dielectric (ILD) layer 122 is formed over the entire top surface of the wafer. This dielectric layer 122 is then selectively removed to form a contact window to expose the source/drain region.
In the conventional process for fabricating an ESD protection device, the source/drain regions are formed as lightly-doped drain (LDD) structures in order to prevent a short channel effect in the internal circuitry. However, these LDD structures result in a higher Zener breakdown voltage which in turn causes the bipolar turn-on speed to slow down and which results in a decrease of the ESD responsiveness of the ESD protection device.
Further, in the conventional process for fabricating ESD protection devices, a thinner gate oxide layer is necessary as the integration of semiconductor devices is increased. This may result in gate thinning and lead to a higher defect density and increased weak point probability.
It is therefore an objective of the present invention to provide a method for forming an electrostatic discharge protection device having increased electrostatic discharge responsiveness.